1. Field of the Invention
This invention relates to integrated circuit structures having local interconnects. More particularly, this invention relates to an integrated circuit structure wherein a local interconnect level is separated from both the underlying substrate and the overlying first metal interconnect level in a manner which permits both the local interconnect level and the first metal interconnect level to bridge over underlying electrically conductive regions without any undue increase in either the capacitance of the structure or the resistance paths through contact openings/vias extending from the substrate to the first metal interconnect layer.
2. Description of the Related Art
Conventionally an integrated circuit structure may be constructed with local interconnects as shown in typical prior art FIG. 1. Typically, such local interconnects are formed in between raised portions of the integrated circuit devices, such as in between gate electrodes. Such local interconnects may be formed using the same conductive material as the filler material, e.g., tungsten, used to fill the contact openings which provide electrical connection to other portions of the integrated circuit device such as the source/drain regions. The local interconnects may also be formed using the same material used in forming the gate electrode, e.g., doped polysilicon. In either case, the material used for the local interconnect characteristically does not possess the same low resistance as the metal used for conventional metal interconnect layers, e.g., aluminum, but is more easily planarized by polishing techniques (particularly when tungsten is used as the local interconnect material). Since such local interconnects are conventionally formed at or about the same level as the gate electrode, they permit some low level electrical connections to be made between adjacent conductive areas at a level lower than the first metal interconnect level. However, since they are typically constructed at the same level as the gate electrodes and have no insulation below separating them from the underlying substrate, their use is limited to the interconnecting of adjacent conductive regions (they cannot bridge over conductive regions) and hence they are referred to as "local interconnects".
FIG. 1 shows a typical prior art integrated circuit structure with a local interconnect formed thereon. In the structure illustrated in FIG. 1, a semiconductor substrate 2 may be provided, by way of example, with several MOS transistors constructed thereon which are electrically isolated from one another by field oxide 6a, and from other devices in substrate 2 by field oxide 6b and 6c. The MOS devices respectively comprise source/drain regions 10 and 12 with a gate electrode 14 therebetween; and source/drain regions 20 and 22 with a gate electrode 24 therebetween. A first dielectric layer 30, formed of a dielectric material such as silicon oxide (SiO.sub.2) and having a thickness of from about 3500 .ANG. to about 5000 .ANG. (after planarization), is deposited over this structure and then planarized back to about the level of gate electrodes 14 and 24, e.g., by an etch step or a chemical mechanical polishing process.
Filled contact openings 32 and 34 are then respectively formed through dielectric layer 30 down to underlying source/drain regions 10 and 22 and then filled with a metal such as tungsten. At the same time, a portion of dielectric layer 30 is etched down to the level of source/drain regions 12 and 20 and field oxide 6b, and then filled with tungsten, to form filled opening 36 which comprises a local interconnect to electrically connect source/drain region 12 with source/drain region 20. Thus, when contact openings 32 and 34 are filled with a conductive material 44, such as tungsten metal, opening 36 is also filled at the same time with the same conductive material, thereby forming local interconnect 36 to electrically interconnect adjacent source/drain regions 12 and 20 together.
After formation of the first level of filled contact openings/vias and the local interconnects, a second dielectric layer 50 (which may also comprise SiO.sub.2 and which may also have a thickness of from about 3500 .ANG. to about 5000 .ANG.) is formed over the structure. A filled via 52 is then formed through dielectric layer 50 to and in registry with underlying filled contact opening 32 to provide electrical contact to source/drain region 10; a filled via 54 is formed through layer 50 to and in registry with gate electrode 14; a filled via 56 is formed through layer 50 to and in registry with gate electrode 24, and a filled via 58 is formed through layer 50 to and in registry with filled contact opening 34 to provide electrical contact to source/drain region 22. Filled vias 52, 54, 56, and 58 are also typically filled with tungsten. A first layer 60 of metal interconnects, illustrated as 60a-60c and typically comprising a metal more highly conductive than tungsten such as aluminum or copper, is then formed over dielectric layer 50 to provide respective electrical contact to filled vias 52, 54, 56, and 58 and to provide interconnections between these regions and other regions (not shown) on the integrated circuit structure.
In this prior art construction it will be readily apparent that first metal interconnect layer 60 can bridge over other underlying conductive regions, e.g., over local interconnect 36, because of the presence of underlying dielectric layer 50. However, it will be equally apparent from examination of FIG. 1, that while underlying local interconnect 36 does permit electrical interconnection between adjacent electrodes or conductive regions below the level of first metal interconnect layer 60, this electrical connection is called a "local interconnect" because only adjacent (or "local") conductive regions (diffusion regions) may be electrically connected together in this manner. This is because local interconnect 36 is formed directly over the surface of substrate 2, i,e, it does not have an underlying dielectric layer unlike first metal interconnect layer 60. This, of course, limits the usefulness of local interconnects.
However, despite the drawbacks of local interconnects, they do have useful functions, even though somewhat limited compared to conventional metal interconnect layers. For example, even when the tungsten material comprising the local interconnect is not deposited over substrate 2 in the same step used to fill contact openings, the contact openings and local interconnect openings may be cut through the dielectric layer at the same time. There are other advantages to forming such a local interconnect at the same level as the contact opening and using the same material as used to fill the contact opening.
For example, it will be noted that the sum of the heights of filled contact opening 32 and filled via 52 from source/drain region 10 to first metal interconnect layer 60 (the combined thickness of dielectric layers 30 and 50) is approximately the same as it would have been had local interconnect 36 not been formed in the structure. That is, the construction of local interconnect 36 in dielectric layer 30 did not lengthen the resistive path through the tungsten filler material from source/drain region 10 to metal interconnect layer 60. Thus, where the use of local interconnects can sometimes eliminate the need for one layer of metal interconnects, the total resistive path through the filled tungsten contact openings/vias in the overall integrated circuit structure may, as a result, be shortened, thus lowering the total resistance in the structure and increasing its speed.
However, it would be even more advantageous if one could utilize local interconnects without limiting their use to only strapping or interconnecting adjacent conductive regions, i.e., if the local interconnect could bridge over conductive regions or other interconnects. An alternative construction, illustrated in FIG. 2, alters the construction of the local interconnect to permit it to bridge or cross over underlying conductive regions.
In FIG. 2, where like structures are shown with like numerals, dielectric layer 30' (which may also comprise SiO.sub.2) is formed over the underlying MOS structures and then planarized back to a thickness which may be the same as the height of gate electrodes 14 and 24, e.g., from about 3500 .ANG. to about 5000 .ANG., but preferably to a thickness slightly (about 500 .ANG. to about 1000 .ANG.) in excess of the height of gate electrodes 14 and 24 for a reason which will be explained below.
Similarly to the structure of FIG. 1, filled contact opening 32' is formed through dielectric layer 30' to underlying source/drain region 10 in substrate 2 and filled contact opening 34' is formed through dielectric layer 30' to source/drain region 22 in substrate 2. However, unlike the structure shown in FIG. 1, a filled contact opening 132 is formed through dielectric layer 30' to source/drain region 12 in substrate 2; and filled contact openings 134 and 136 are respectively formed through dielectric layer 30' to gate electrode 14 and gate electrode 24. In each case, the filled contact openings may be filled with tungsten, as in the previous embodiment described for FIG. 1.
After formation of filled contact openings 32', 34', 132, 134, and 136 in dielectric layer 30', a further dielectric layer 50' (which may also comprise SiO.sub.2 and which may have the same thickness range as layer 50) is formed over dielectric layer 30' and the filled contact openings therein. A filled via 52' is formed in dielectric layer 50' extending down to (and in registry with) underlying filled contact opening 32', a filled via 54' is formed in dielectric layer 50' down to (and in registry with) underlying filled contact opening 134 over gate electrode 14, and a filled via 58' is formed in dielectric layer 50' down to (and in registry with) underlying filled contact opening 34'.
However, in this embodiment, a local interconnect 156 is formed in second dielectric layer 50' over (and in registry with) underlying filled contact opening 132 and filled contact opening 136, thereby connecting together source/drain region 12 and gate electrode 24. Furthermore, unlike the previous embodiment of FIG. 1, local interconnect 156 in FIG. 2 is shown bridging source/drain region 20 (electrical contact can be made to source/drain region 20 at another non-illustrated point in the structure along an axis perpendicular to the plane of the figure). Thus, this embodiment now permits the flexibility of use of the local interconnect which is lacking in the structure of FIG. 1. Furthermore, when the thickness of first dielectric layer 30' exceeds the height of gate electrodes 14 and 24, local interconnect 156 can even bridge such raised gate electrodes.
Nevertheless, there is a drawback with the use of the FIG. 2 structure which, at least in part, negates the advantages of the FIG. 2 structure over the FIG. 1 structure. This disadvantage is illustrated in FIG. 2 by the formation of the first metal interconnect layer 60' directly over second dielectric layer 50' as shown. Thus, illustrated individual metal interconnects 60a'-60d' are formed directly above second dielectric layer 50'. This puts the undersurface of first metal interconnect 60b', for example, directly in contact with the upper surface of local interconnect 156. Those skilled in the art will readily appreciate that the drawback in FIG. 1 of placing local interconnect 36 directly above substrate 2 (so that conductive regions in substrate 2 cannot be bridged by the local interconnects) has now simply been transferred to the interface between the local interconnect layer and the first metal interconnect layer. That is, now the first layer of metal interconnects cannot bridge over the local interconnects. This is actually a more serious problem than the problem encountered in the structure of FIG. 1, since the first metal interconnect layer is conventionally a more crowded layer with many more interconnects than at the local interconnect level, and the inability of the first metal interconnect level to cross over underlying local interconnects is a disability which cannot and will not be tolerated by design (layout) engineers.
While it might seem to be obvious to simply add another dielectric layer to the FIG. 2 structure, between the local interconnect layer and the first metal interconnect layer, to solve the bridging problem, this, too, cannot be tolerated because the presence of another dielectric layer between the first metal interconnect and the substrate results in the need to provide another layer of tungsten-filled vias through this third dielectric layer, thus adding to the cost and complexity of the structure as well as increasing the defect density.
Thus, it remains a desire and goal to provide an integrated circuit structure with local interconnects and a first metal interconnect layer wherein both the local interconnect layer and the first metal interconnect layer may be capable of bridging over underlying conductive region in the integrated circuit structure without, however, substantial addition to either the resistance or the capacitance of the structure.